CPU, GPU, TPU, NPU, LPU, DPU & QPU Explained

The CPU is general-purpose computing: operating systems, I/O, databases, branch-heavy logic, and orchestrating everything else in the stack. It's built around a small number of powerful cores (typically 4–64), high clock speeds, deep cache hierarchies, and out-of-order execution — optimized for doing many different kinds of sequential work fast and flexibly, not for doing one kind of math millions of times in parallel.

The 2026 generation keeps pushing AI capability into the CPU itself. Intel's Core Ultra Series 3 ("Panther Lake") ships with up to 16 cores, clocks to 5.1GHz, and an integrated NPU and Arc GPU for always-on edge AI without a discrete accelerator. AMD's EPYC and Ryzen lines take the equivalent approach for servers and desktops, while Apple's M-series and ARM's Neoverse cores extend the same general-purpose role into laptops and cloud infrastructure. In the data center, NVIDIA's Grace CPU exists specifically to feed GPUs at high bandwidth rather than to compute independently.

Where a CPU has dozens of cores, a GPU has thousands of simpler ones running the same operation across massive amounts of data simultaneously (SIMT execution). That structure — originally built for rendering pixels — turns out to be exactly what neural network training and inference need, since both are dominated by matrix multiplication.

NVIDIA's Blackwell architecture (208 billion transistors, built on TSMC's custom 4NP process) anchors the current generation: the GB200 NVL72 connects 36 Grace CPUs and 72 Blackwell GPUs into a single rack-scale system behaving as one giant GPU, and Blackwell Ultra is built specifically to cut inference cost for agentic AI. A key part of the story is the precision cascade — FP32 → FP16/BF16 → FP8 → NVFP4/INT8 — where each step trades numerical precision for speed, memory footprint, and lower cost per token. AMD's Instinct MI300X/MI355X and Intel's Gaudi accelerators compete in the same space.

Google designed the TPU as a custom ASIC around one job: matrix and tensor math, using a "systolic array" that streams data through thousands of arithmetic units without the constant memory reads and writes a general-purpose chip needs. That narrower focus buys efficiency a GPU can't match for the workloads it targets — at the cost of being tied to Google Cloud and its software stack (JAX, PyTorch/XLA, TensorFlow).

Ironwood, Google's 7th-generation TPU, is generally available in 2026: 9,216 liquid-cooled chips per pod delivering 42.5 exaFLOPS, roughly four times the per-chip performance of the previous Trillium generation. Google has also previewed two purpose-split successors — TPU 8t for large-scale pre-training and TPU 8i, optimized specifically for low-latency inference with an 80% performance-per- dollar improvement over prior generations.

NPUs are small, low-power blocks built into phone, laptop, and car chipsets to run AI inference locally — keyboard prediction, photo processing, voice transcription, on-device summarization — without a round trip to the cloud. They're tuned for low- precision (INT8/INT4) multiply-accumulate math at a fraction of a GPU's power draw.

Qualcomm's Snapdragon 8 Elite Gen 5 Hexagon NPU reaches roughly 100 TOPS, and its Snapdragon X2 Elite Extreme for laptops sits around 80–85 TOPS. Apple takes a different tack: the M-series Neural Engine (38–45 TOPS on M4/M5) leans on unified memory architecture rather than raw TOPS, and Apple stopped quoting a TOPS figure with M5 in favor of GPU-based Neural Accelerators. That split matters: raw TOPS comparisons across chips with different memory architectures are frequently misleading — real-world inference speed depends as much on memory bandwidth as on compute throughput.

The LPU is a vendor-specific term coined by Groq, not a universal processor category the way CPU or GPU are. It uses on-chip SRAM instead of external HBM memory, trading total capacity for deterministic, extremely low-latency execution — a good match for the sequential, one-token-at-a-time decode phase of LLM inference, but not for training or for vision and video workloads.

The architecture's significance grew sharply in late 2025, when NVIDIA licensed Groq's LPU architecture in a roughly $20 billion deal; Groq now positions itself as "the premier neocloud for fast inference," with its LPU-derived LPX technology running alongside NVIDIA's next-generation GPUs rather than competing with them. The lesson generalizes beyond Groq: fast and affordable inference no longer requires a single monolithic chip — it increasingly comes from pairing a latency-specialized decode engine with a general-purpose GPU.

A DPU is best understood as a SmartNIC with its own CPU cores and operating system, sitting between the network and the server. It offloads networking, storage virtualization, and security — encryption, firewalling, threat detection — so CPUs and GPUs stay free for actual compute instead of moving and guarding data.

NVIDIA's BlueField-4, targeted for 2026 as part of the Vera Rubin platform, delivers 800Gb/s throughput with roughly six times the compute of its BlueField-3 predecessor (already in production at 400Gb/s), and is purpose-built to power AI-native storage and real-time threat detection at gigascale. AMD's Pensando line occupies the same category. As AI clusters move ever-larger volumes of training data, checkpoints, and KV-cache between nodes, the DPU has become as central to cluster design as the GPU itself.

A QPU isn't a faster version of anything above — it's a fundamentally different computing model. Instead of classical bits, it manipulates qubits using superposition (existing in a combination of states at once) and entanglement (correlating qubits so their states depend on each other), letting certain problems be explored across many possibilities simultaneously rather than one at a time. That's suited to specific problem classes — combinatorial optimization, cryptography, molecular and materials simulation, some search algorithms — not general-purpose computing, and a QPU won't replace a CPU or GPU on your desk.

The field is still in the NISQ era (noisy intermediate-scale quantum): qubits are error-prone, systems need cryogenic cooling, and every QPU today runs tethered to classical control hardware. IBM's Nighthawk processor, unveiled in late 2025, gives IBM Quantum's platform access to 100+ qubit systems, and IBM reported a demonstration of quantum advantage through trusted quantum computation in mid-2026, with a roadmap targeting fault-tolerant systems running millions of quantum gates by decade's end. Google (Willow), IonQ, Rigetti, and D-Wave pursue the same goal through different physical approaches — superconducting circuits, trapped ions, and quantum annealing among them. For most enterprises, QPUs remain an exploratory research tool today rather than a production one.